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[VHDL-FPGA-Verilog] we

Description: 用VHDL写的5级流水线的回写阶段，绝对好用-Using VHDL written five stage pipeline write-back, absolutely easy to use
Platform: | Size: 1024 | Author: rsee | Hits:

[VHDL-FPGA-Verilog] PIPE_LINING_CPU_TEAM_24

Description: 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,rs,rt slti rt,rs,imm sltiu rt,rs,imm sllv rd,rt,rs sra rd,rt,shamt blez rs,imm j target lwl rt,offset(base) lwl rt,offset(base) lw rt,imm(rs) sw rt,imm(rs) 在本设计中，采取非常良好的模块化编程风格，共分十三个主要模块PIPE_LINING_CPU_TEAM_24.v为顶层实体文件，对应为PIPE_LINING_CPU_TEAM_24模块作为顶层实体模块，如下： ifetch.v、regdec.v、exec.v、mem.v、wr.v分别实现五个流水段； cpuctr.v用于产生CPU控制信号； ALU.v用于对操作数进行相应指令的运算并输出结果； DM.v数据存储器 IM.v指令存储器 datareg.v数据寄存器堆 extender.v位扩展 yiwei_32bits.v 实现32位四种移位方式的移位器 在顶层实体中，调用ifetch.v、regdec.v、exec.v、mem.v、wr.v这五个模块就实现了流水线CPU。顶层模块的结构清晰明了。对于学习verilog编程非常有用- Quatus II compiled by the environment, using Verilog HDL language to achieve a five-stage pipeline CPU. To complete the following 22 commands (not considering the virtual address and Cache, and the default mode for the small end): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo rd, rs clz rd, rs slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwl rt, offset (base) lw rt, imm (rs) sw rt, imm (rs) In this design, take a very good modular programming style, is divided into 13 main modules PIPE_LINING_CPU_TEAM_24.v for the top-level entity file, the corresponding module as a top-level entity for the PIPE_LINING_CPU_TEAM_24 modules, as follows: ifetch.v, regdec.v, exec.v, mem.v, wr.v water were to achieve the five paragraph cpuctr.v used to generate CPU control signal ALU.v accordingly
Platform: | Size: 4946944 | Author: 石 | Hits:

[VHDL-FPGA-Verilog] PipeLine.tar

Description: Verilog实现MIPS五段流水线，22条指令（基本算术、移位和load、store指令），模块化设计，含注释-Verilog realization of five-stage pipeline MIPS 22 instructions (basic arithmetic, shift, and load, store instructions), modular design, with annotations
Platform: | Size: 2929664 | Author: czl | Hits:

[VHDL-FPGA-Verilog] pipelined-mips-cpu

Description: 用verilog语言描述了MIPS的5级流水线。-Language described by verilog MIPS 5-stage pipeline.
Platform: | Size: 171008 | Author: jack chen | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
Platform: | Size: 2048 | Author: dylan | Hits:

[VHDL-FPGA-Verilog] Reconfigurablefliter

Description: 自己编写的SystemC源代码，拥有五级流水线的可重构图像滤波器，支持两种图像滤波算法，中值滤波和邻域平均滤波，支持算法配置-I have written SystemC source code, the reconfigurable image filter has a five-stage pipeline, supports two types of image filtering algorithms, median filtering and neighborhood average filter support algorithm configuration
Platform: | Size: 18989056 | Author: SuperWang | Hits:

[VHDL-FPGA-Verilog] cpu_design

Description: FPGA MIPS架构CPU，五段流水线功能，ISE开发，verilog语言，可综合，模拟结果正确，内含设计报告-FPGA MIPS CPU, simple five-stage pipeline function, developed by ISE, using verilog language
Platform: | Size: 2428928 | Author: leo | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括：取指模块，译码模块，执行模块，访存模块，写回模块，寄存器组模块，控制相关检测模块，Forwarding模块。该CPU在TEC-CA实验平台上运行，并且通过Debugcontroller软件进行单步调试，实验表明，该流水线CPU消除了控制相关、数据相关和结构相关。-Using vhdl hardware description language development environment under quartus II design and implementation of an independent design and implementation of a five-stage pipeline RISC-based CPU' s. The water CPU include: fetch module, decoding module, execution modules, memory access module, the write-back module, the register set of modules, control relevant to the detection module, Forwarding module. The CPU in the TEC-CA experimental platforms, and single-step debugging through Debugcontroller software, experiments show that the pipelined CPU eliminates the control-related, data-related and structurally related.
Platform: | Size: 822272 | Author: wang | Hits:

[JSP/Java] Pipeline

Description: 用图形界面演示模型机的指令序列在5级流水线上的执行过程。使用高级语言Java，在Eclipse环境下开发流水线的仿真程序。实现针对任意的无相关模型机指令序列（包括数据前推、load前推并解决控制相关），能单步显示出每个时钟周期流水线上指令的执行情况，具体包括：时钟周期及编号、各级流水线寄存器的内容、各级流水线的控制信号。- Graphical interface demo model machine instruction sequence is d on five pipeline. Using high-level languages Java, Eclipse development environment in the pipeline simulation program. Achieve no correlation model for any sequence of machine instructions (including data before pushing, pushing and resolved before the load control related), to show the implementation of a single step on each clock cycle instruction pipeline, including: number of clock cycles and each content-stage pipeline registers, control signal line levels.
Platform: | Size: 26624 | Author: 孙雅楠 | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 五级流水线.期末的project,写了很详细的注释，应该能看得懂了吧。-Five-stage pipeline. Closing the project, wrote a very detailed notes, should be able to understand it.
Platform: | Size: 1454080 | Author: susht | Hits:

[VHDL-FPGA-Verilog] mips

Description: 基于mips架构的五级流水线硬件实现。使用verilog-Based on the five-stage pipeline hardware architecture mips
Platform: | Size: 4096 | Author: 毕翔宇 | Hits:

[VHDL-FPGA-Verilog] pcpu_handle_mem

Description: Verilog实现五级流水线CPU，hazard以及时序功能已经实现。-Realize five-stage pipeline CPU
Platform: | Size: 11389952 | Author: llly | Hits:

[assembly language] code

Description: 汇编语言16位五级流水线，已实现Hazard处理-Assembly Language 16 five-stage pipeline, processing has been implemented Hazard
Platform: | Size: 10240 | Author: 苏娇 | Hits:

[VHDL-FPGA-Verilog] CPU-Pipeline

Description: 五级流水线的CPU的工程文件，在vivado上用verilog语言实现，包括串口，可进行简单的数学加法运算。(Five-stage pipeline CPU project files, including the serial port. vivado Verilog language. This CPU can do simple mathematical addition.)
Platform: | Size: 14336 | Author: Si Cheng | Hits:

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